Synchronization of interrupts with data packets

ABSTRACT

A method and apparatus for conveying data over a packet-switching network ( 26 ). Data are received from a peripheral device ( 25 ) for transmission via the network to a memory ( 22 ) associated with a central processing unit (CPU) ( 21 ), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface ( 32 ) serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation in part of application Ser. No. 09/559,352, filedApr. 27, 2000, now U.S. Pat. No. 6,243,787. This application claims thebenefit of U.S. Provisional Patent Application 60/152,849, filed Sep. 8,1999, and of U.S. Provisional Patent Application 60/175,339, filed Jan.10, 2000. Both of these co-pending applications are assigned to theassignee of the present patent application and are incorporated hereinby reference.

FIELD OF THE INVENTION

The present invention relates generally to computing systems, andspecifically to systems that use packet-switching fabrics to connect acomputer host to peripheral devices.

BACKGROUND OF THE INVENTION

In current-generation computers, the central processing unit (CPU) isconnected to the system memory and to peripheral devices by a parallelbus, such as the ubiquitous Peripheral Component Interface (PCI) bus. Asdata path-widths grow, and clock speeds become faster, however, theparallel bus is becoming too costly and complex to keep up with systemdemands. In response, the computer industry is moving toward fast,packetized, serial input/output (I/O) bus architectures, in whichcomputing hosts and peripheral are linked by a switching network,commonly referred to as a switching fabric. A number of architectures ofthis type have been proposed, including “Next Generation I/O” (NGIO) and“Future I/O” (FIO), culminating in the “InfiniBand” architecture, whichhas been advanced by a consortium led by a group of industry leaders(including Intel, Sun, Hewlett Packard, IBM, Compaq, Dell andMicrosoft). Storage Area Networks (SAN) provide a similar, packetized,serial approach to high-speed storage access, which can also beimplemented using an InfiniBand fabric.

In a parallel bus-based computer system, when a peripheral device needsto deliver data to the CPU, it typically writes the data to the memoryover the bus, using direct memory access. When the peripheral hasfinished writing, it asserts an interrupt to the CPU on one of theinterrupt lines of the bus. Bus arbitration ensures that the CPU willnot attempt to read the data from the memory until the writing of thedata is complete. On the other hand, when the peripheral device and theCPU are connected by a packet-switching fabric, such as an InfiniBandfabric, they operate asynchronously. Furthermore, the data sent to thememory and the interrupt to the CPU travel over different paths, orchannels. Typically, a separate line or channel is provided to connectthe interrupt pin of the peripheral device to an interrupt controller ofthe CPU, bypassing the switching fabric. Therefore, there is no a prioriassurance that all of the data will have been written to the memorybefore the CPU begins reading.

The “race” between the interrupt path and the data path can result inerrors (as when a CPU read stalls the data). Care must therefore betaken to synchronize data and interrupt handling and to make sure thatthe data have been completely written to the memory before the CPUattempts to read it.

A common solution in this situation is to program the CPU to access theperipheral device before accessing the memory, typically by performing a“configuration read” from the peripheral device. In this mode ofoperation, after the peripheral device has asserted the interrupt to theCPU (indicating that the last item of data has been sent to the memory),the CPU issues a read request through the switching fabric, to read aninterrupt cause register in the peripheral device. The peripheral deviceresponds to the read request by sending a packet containing theinterrupt cause to the CPU over the same channel as it used to send thedata to the memory. Since packets are ordered within a channel, theresponse to configuration read arrives at the CPU after all of theprevious writes have been flushed to memory. The CPU begins to read thedata from the memory only after it has received the interrupt causepacket back from the peripheral device. The configuration read thusserves two crucial purposes: it provides the CPU with the causeinformation that it needs in order to serve the interrupt, and itensures that the CPU reads the memory only after all of the data havebeen written there.

This scheme has a number of serious performance drawbacks, however.Every interrupt sent by the peripheral device necessitates an additionalexchange of messages through the switching fabric between the CPU andperipheral device. The exchange adds substantial latency—typically 10microseconds or more—every time the CPU must service an interrupt.Furthermore, since configuration reads are used as synchronizationbarriers, the CPU is stalled from the moment the configuration readrequest is issued until its response has arrived. Valuable CPU time istherefore wasted waiting for the interrupt cause to be retrieved.

U.S. Pat. No. 5,689,713, whose disclosure is incorporated herein byreference, describes a method for interrupt request handling in apacket-switched computer system. The system may include a number ofinterrupt sources, which direct interrupts to any of a number ofinterrupt handlers. A system controller acts as an intermediary betweeninterrupting devices and “interruptees.” It includes an interrupt queuecoupled to each interrupt source for receiving multiple interruptrequests, and an output queue coupled to each interrupt handler Thecontroller thus enables asynchronous data from multiple sources to beconveyed across a packet-switched interconnection, while providing adedicated channel for interrupts associated with the data packets.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved methodand system for passing data packets and associated interrupts through aswitching fabric.

It is a further object of some aspects of the present invention toprovide a method and system for communication between a CPU andperipheral devices via a switching fabric that ensures propersynchronization between data and interrupts transmitted over the fabric.

It is still a further object of some aspects of the present invention toprovide a method and system for communication between a CPU andperipheral devices via a switching fabric that reduces latency andprocessing time required for servicing of interrupts by the CPU.

In preferred embodiments of the present invention, a CPU and aperipheral device are linked to a packet-switching fabric by respectivehost and target network interfaces. The target interface receives dataover a local bus from the peripheral device, for transmission in theform of packets to a system memory associated with the CPU. Aftersending the data, the peripheral device asserts an interrupt. Theinterrupt from the device is connected to an interrupt input of thetarget interface, rather than directly to the CPU or to a central systemcontroller, as in systems known in the art. In response to theinterrupt, the target interface reads the interrupt cause from theperipheral device, and then sends a special interrupt packet, includingthe interrupt cause, to the host interface. Preferably, the targetinterface sends the interrupt packet on the same channel as it sent thedata packets, i.e., over the same “virtual lane,” or route, and with thesame priority as the data packets. It thus assures that the hostinterface will receive the interrupt packet only after it has receivedall of the preceding data packets.

Upon receiving the interrupt packet, the host interface places theinterrupt cause in a predefined register in the memory. An interruptsignal is then sent from the host interface to an interrupt input of theCPU. Upon receiving the signal, the CPU checks to ensure that the hostinterface has finished writing all of the data from the peripheraldevice to the memory. This check serves a similar purpose to theconfiguration read described in the Background of the Invention. Onlyafter completing the check does the CPU read the interrupt cause andbegin processing the data in the memory. The CPU performs all of thesesteps locally, communicating with the host interface and memory over alocal system bus, with latency on the order of nanoseconds, rather thanhaving to exchange messages with the peripheral device through theswitching fabric, taking many microseconds. As a result, interruptresponse latency is minimized, and the CPU does not waste precious timeand resources waiting for the configuration read response.

In preferred embodiments of the present invention, the switching fabriccomprises an InfiniBand network, and the host and target interfacesrespectively comprise host and target channel adapters. It will beappreciated, however, that the principles of the present invention maysimilarly be applied to transmission of interrupts through substantiallyany packet-switched network.

There is therefore provided, in accordance with a preferred embodimentof the present invention, a method for conveying data over apacket-switching network, including:

-   -   receiving data from a peripheral device for transmission via the        network to a memory associated with a central processing unit        (CPU);    -   receiving an interrupt signal from the peripheral device        associated with the data;    -   sending one or more data packets containing the data over the        network to a host network interface serving the memory and the        CPU; and    -   sending an interrupt packet over the network to the host network        interface, responsive to which an interrupt input of the CPU is        asserted only after the one or more data packets have arrived at        the host network interface.

Typically, receiving the data includes receiving parallel data over alocal bus from the peripheral device. Additionally or alternatively,receiving the data includes receiving data to be written to the memoryby direct memory access.

Preferably, sending the interrupt packet includes reading a cause of theinterrupt from the peripheral device, and incorporating the cause in theinterrupt packet. Further preferably, the method includes receiving theinterrupt packet at the host network interface, and writing the cause toa predetermined address in the memory, to be read by the CPU after theinterrupt input is asserted.

In a preferred embodiment, sending the interrupt packet includes sendingthe interrupt packet after receiving an acknowledgment from the memorythat the data have been written thereto.

Preferably, sending the one or more data packets includes sending thedata packets over a selected channel through the network, and sendingthe interrupt packet includes sending the interrupt packet over theselected channel following the data packets.

Further preferably, the method includes:

-   -   receiving the data packets and the interrupt packet at the host        network interface;    -   conveying the data in the packets for delivery to the memory        over a local bus coupling the host network interface to the        memory and the CPU; and    -   notifying the CPU when all of the data have been conveyed.

Most preferably, conveying the data in the packets includes passing thedata to a system controller on the bus, and notifying the CPU includesinforming the CPU when an acknowledgment is received by the host networkinterface from the system controller, typically by asserting theinterrupt input of the CPU after the acknowledgment from the systemcontroller has been received. Additionally or alternatively, notifyingthe CPU includes asserting the interrupt input of the CPU responsive toreceiving the interrupt packet at the host network interface.

There is also provided, in accordance with a preferred embodiment of thepresent invention, network interface apparatus, including:

-   -   a target channel adapter, which is operative to receive data        from a peripheral device for transmission via a packet-switching        network to a memory associated with a central processing unit        (CPU) and to send one or more data packets containing the data        over the network to a host network interface serving the memory        and the CPU; and    -   a target interface processor, adapted to receive an interrupt        signal from the peripheral device associated with the data, and        to send an interrupt packet over the network to the host network        interface, responsive to which an interrupt input of the CPU is        asserted only after the one or more data packets have arrived at        the host network interface.

There is further provided, in accordance with a preferred embodiment ofthe present invention, network interface apparatus, including:

-   -   a host channel adapter, which is operative to receive data        packets transmitted over a packet-switching network from a        peripheral device, and to convey data from the packets for        delivery to a memory associated with a CPU over a local bus that        is coupled to the memory and the CPU, and further to receive an        interrupt packet sent over the network responsive to an        interrupt signal asserted by the peripheral device after sending        the data to the network; and    -   a host interface processor, adapted, responsive to the interrupt        packet, to notify the CPU when all of the data have been        conveyed to the local bus.

Preferably, the target and host channel adapters include InfiniBandadapters.

The present invention will be more fully understood from the followingdetailed description of the preferred embodiments thereof, takentogether with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram that schematically illustrates a computingsystem based on a packet-switching fabric, in accordance with apreferred embodiment of the present invention;

FIG. 2 is a flow chart that schematically illustrates a method fortransmitting data from a peripheral device to a CPU in the system ofFIG. 1, in accordance with a preferred embodiment of the presentinvention; and

FIG. 3 is a flow chart that schematically illustrates a method forprocessing data received by the CPU in the system of FIG. 1, inaccordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 is a block diagram that schematically illustrates a computingsystem 20 built around a switching fabric 26, in accordance with apreferred embodiment of the present invention. The switching fabricpreferably comprises an InfiniBand fabric, as described in theBackground of the Invention, and some of the terms used hereinbelow arespecific to the InfiniBand architecture. It will be understood, however,that the system architecture and methods of communication describedherein are in no way limited to InfiniBand, and that other switchingfabrics, as are known in the art, may be configured to handle and conveyinterrupts in a similar manner.

A CPU 21 is coupled to communicate via a system bus 52 with a systemcontroller 24 and a system memory 22, as is known in the art. Typically(although not necessarily), the CPU comprises an Intel Pentiumprocessor, and bus 52 is a proprietary bus used in conjunction with thisprocessor, System controller 24 is coupled to a standard I/O bus 50,such as a PCI bus, for the purpose of communicating with peripheraldevices, such as I/O adapters of various types. One such peripheraldevice 25 is shown in FIG. 1 by way of example, but in practicalapplications, system 20 typically comprises multiple peripheral devicesand, possibly, multiple CPUs. Peripheral device 25 includes an interruptoutput 48, which it asserts in order to gain the attention of the CPU,In systems known in the art, interrupt output 48 is connected directlyto an interrupt controller 38, such as an Intel 8259 device, whichactuates an appropriate interrupt input 27 of CPU 21 when the interruptis asserted. In system 20, however, interrupt output 48 and input 27 arelinked only through fabric 26, as described hereinbelow.

Bus 50 is coupled to fabric 26 by a host network interface unit 28. Thisunit comprises a host channel adapter (HCA) 32, which interfaces withbus 50 and converts data between packet and parallel forms.Alternatively, the HCA may be designed to interface with system bus 52.A switch 30 links the HCA to one or more core switches in the fabric.Ordinarily, data in packets received by switch 30 from fabric 26 arepassed through HCA 32 to bus 50. An exception is made, however, formanagement packets, which are packets that carry a special headeridentifying themselves as such and including a local identifier (LID)address of either switch 30 or HCA 32. These packets contain controlinstructions for the switch or HCA. They are placed in a dedicatedregister of the switch or HCA, as appropriate, which then attempts todecode the instructions and carry them out. Typically, the processingcapabilities of the switch and HCA are very limited, and they areassisted by a fabric service agent (FSA), as described below, in dealingwith at least some of these management packets.

A host interface unit controller 36 acts as the FSA in interface unit28. The controller preferably comprises a microprocessor with randomaccess memory (RAM) for software code and data, communicates with HCA 32and switch 30. Alternatively, the controller may comprise a hard-wiredhardware element or digital signal processor. When HCA 32 or switch 30receives a management packet that it cannot decode, it passes the packetto the controller. The controller decodes the packet, preferably basedon suitable software stored in its code RAM. It then takes whateveraction is called for by the packet, such as giving appropriateinstructions to HCA 32 or switch 30. When the HCA receives an interruptpacket, as described below, the actions taken by controller 36 alsoinclude signaling interrupt controller 38 via an interrupt output ofunit 28, so as to actuate interrupt input 27 of CPU 21.

Although for simplicity, only a single interrupt line from unit 28 tocontroller 38 is shown in FIG. 1, the unit preferably comprises multipleinterrupt lines These lines can be actuated selectively by controller 36so as to send multiple, different interrupts to CPU 21 depending on thecontent of interrupt packets received by the HCA. Alternatively oradditionally, the different interrupt lines may be used to signal otherhost devices that are linked to bus 50.

Peripheral device 25 is coupled to fabric 26 by a target networkinterface unit 40, similar in structure to unit 28. A target channeladapter (TCA) 42 in unit 40 interfaces via an I/O bus 53 with device 25.Typically, although not necessarily, bus 53 comprises a PCI bus, likebus 50. A switch 44 links the TCA to the switching fabric. A target unitcontroller 46, similar to controller 36, acts as FSA to TCA 42 andswitch 44 and also has a suitable input to receive signals frominterrupt output 48 of device 25.

FIG. 2 is a flow chart that schematically illustrates a method by whichtarget interface unit 40 processes and transmits data from peripheraldevice 25 to HCA 32 over fabric 26, in accordance with a preferredembodiment of the present invention. At a data writing step 60, device25 writes data via bus 53 to TCA 42, to be conveyed by direct memoryaccess to memory 22. The peripheral device assigns a priority to thedata to be transmitted and informs the TCA of this priority. At a datasending step 62, the TCA packetizes the data and sends it over fabric 26to the address of HCA 32, with the priority assigned by the peripheraldevice. A packet header instructs the HCA to write the data to memory22. Preferably, the TCA negotiates with switch 44 and fabric 26 toassign a fixed route for all of the packets through the fabric. Such aroute, together with the priority of the packets, is referred to hereinas a channel. InfiniBand specifies that packets travelling over the samechannel are always kept in their original order.

When device 25 has finished posting to TCA 42 all of the data that ithas to send, it asserts interrupt output 48, at an interrupt assertionstep 64. At the same time, the peripheral device places the cause forthe interrupt (in this case, to instruct CPU 21 to read the data frommemory 22) in an interrupt cause register 49. In systems known in theart, when the CPU receives the interrupt, it must communicate with theperipheral device in order to read this register. In system 20, however,the interrupt signal is received by controller 46, which instructs TCA42 to read the interrupt cause from register 49, at a cause reading step66.

Based on the interrupt cause information read by the TCA, controller 46constructs an interrupt packet containing the interrupt causeinformation, at an interrupt packet sending step 68. The interruptpacket is a management packet addressed to the LID of HCA 32. It ispreferably sent by controller 46 over the same channel, or virtual lane,as the data packets, after the last of the data packets has been sent.The interrupt packet also identifies the data with which the interruptis associated. As a result, when the interrupt packet arrives at itsdestination, controller 36 will be able to generate an interrupt to CPU21 that is associated with the appropriate memo write, as describedbelow. Controller 46 assures than interrupt packet is sent to the fabricafter all of the data packets have already been accepted for sending. Itthus ensures that HCA 32 will receive the interrupt packet only after ithas received all of the data packets.

As an alternative, controller 46 may delay sending the interrupt packetuntil TCA 42 receives an acknowledgment from memory 22 that it hasreceived all of the data. This approach introduces additional delaybefore CPU 21 can receive and act upon the interrupt, but it obviatesthe need to ensure that the interrupt packet is routed over the samechannel as the data packets. Such an approach may be called for inparticular when switching fabric 26 comprises a network in whichconsistent routing and ordering are not necessarily maintained amongsuccessive packets. This approach can also be used when the interruptpath and data path are not the same, and fork at an earlier stage thanin FIG. 1. Such path incongruity may occur, for example, when the devicewriting data to the memory is different from the device asserting theinterrupt to the CPU. Sometimes it is also desirable to send interruptson different (high-priority) routes, because data routes can becongested, causing interrupt messages to get stuck behind data.

FIG. 3 is a flow chart that schematically illustrates a method by whichdata and accompanying interrupt packets are received and processed byhost interface unit 28 and CPU 21, in accordance with a preferredembodiment of the present invention. At a packet reception step 70, HCA32 receives the data and interrupt packets sent from target interfaceunit 40. The HCA posts the data in the data packets via bus 50 to abuffer 58 of system controller 24. The system controller proceeds towrite the data from its buffer to the appropriate addresses in memory22, as is known in the art. The HCA passes the interrupt packet tocontroller 36 for decoding, at an interrupt processing step 72. Thecontroller extracts the cause of the interrupt and posts thisinformation, via HCA 32, to an interrupt cause register 56 in memory 22.

Before CPU 21 services the interrupt represented by the interruptpacket, it is necessary to ensure that all of the associated data havebeen written to memory 22, at a delivery completion step 74. In the casethat controller 46 of target interface unit 40 is programmed to send theinterrupt packet only after receiving the acknowledgment from memory 22,as described above, this problem is already solved. Otherwise,controller 36 preferably waits to assert the interrupt until systemcontroller 24 has acknowledged to HCA 32 that it has received all of thedata. In response to this acknowledgment, controller 36 sends aninterrupt signal to interrupt controller 38, at an interrupt assertionstep 76. The interrupt controller actuates interrupt input 27 of CPU 21,to inform the CPU that an interrupt has arrived from HCA 32. In responseto the interrupt, the CPU preferably sends a dummy read command to theHCA, in order to ensure that buffer 58 is flushed to memory 22 beforethe CPU itself begins to process the data in the memory.

As a further alternative, as long as it is assured that the interruptpacket reached HCA 32 after the last of the data packets (which will bethe case when all of the packets are sent over the same channel, asdescribed above), controller 36 may send the interrupt signal tointerrupt controller 38 immediately, without waiting for anacknowledgment from system controller 24. In this case, upon receivingthe interrupt, CPU 21 preferably sends a “fence” command to HCA 32. Thiscommand instructs the HCA to mark the last packet currently in itsreceive queue, and to inform the CPU when this last packet has beenwritten to system controller 24. At this point, the CPU can send itsdummy read command and begin processing the data in the memory.

Once it is assured that all of the relevant data have reached theirdestination in memory 22, CPU 21 reads the cause of the currentinterrupt from register 56, at a cause reading step 78. Based on thisinformation, the CPU processes the data that peripheral device 25 hasplaced in the memory, at a data processing step 80. Unlike methods ofinterrupt processing known in the art, all of the steps in the method ofFIG. 3 are carried out locally, typically over busses 50 and 52, withoutthe need for messages to traverse fabric 26.

It will be appreciated that the preferred embodiments described aboveare cited by way of example, and that the present invention is notlimited to what has been particularly shown and described hereinabove.Rather, the scope of the present invention includes both combinationsand subcombinations of the various features described hereinabove, aswell as variations and modifications thereof which would occur topersons skilled in the art upon reading the foregoing description andwhich are not disclosed in the prior art.

1. A method for communication between a peripheral device and a centralprocessing unit (CPU), comprising: receiving data from the peripheraldevice for transmission to a memory associated with the CPU; receivingan interrupt signal from the peripheral device associated with the data;sending one or more data packets containing the data over a switchedserial connection to a host interface serving the memory and the CPU;and sending an interrupt packet over the switched serial connection tothe host interface, responsive to which an interrupt input of the CPU isasserted only after the one or more data packets have arrived at thehost interface; wherein receiving the data comprises receiving data tobe written to the memory by direct memory access.
 2. A method forcommunication between a peripheral device and a central processing unit(CPU), comprising: receiving data from the peripheral device fortransmission to a memory associated with the CPU; receiving an interruptsignal from the peripheral device associated with the data; sending oneor more data packets containing the data over a switched serialconnection to a host interface serving the memory and the CPU; andsending an interrupt packet over the switched serial connection to thehost interface, responsive to which an interrupt input of the CPU isasserted only after the one or more data packets have arrived at thehost interface; wherein sending the one or more data packets comprisessending the data packets over a selected lane through a packet-switchednetwork, and wherein sending the interrupt packet comprises sending theinterrupt packet over the selected lane following the data packets. 3.Communication apparatus, comprising: a serial interface, which isoperative to receive data from a peripheral device and to transmit thedata in the form of one or more data packets via a switched serialconnection to a host interface, for writing to a memory associated witha central processing unit (CPU) served by the host interface; and aninterrupt processor, adapted to send an interrupt packet over theswitched serial connection to the host interface to signal that the datahave been transmitted, thus causing an interrupt input of the CPU to beasserted only after the one or more data packets have arrived at thehost interface; wherein the interrupt processor is operative to receivea cause of the interrupt from the peripheral device, and to incorporatethe cause in the interrupt packet.
 4. Apparatus according to claim 3,wherein the host interface is adapted to receive the interrupt packetand to write the cause to a predetermined address in the memory, to beread by the CPU after the interrupt input is asserted.
 5. Communicationapparatus, comprising: a serial interface, which is operative to receivedata from a peripheral device and to transmit the data in the form ofone or more data packets via a switched serial connection to a hostinterface, for writing to a memory associated with a central processingunit (CPU) served by the host interface; and an interrupt processor,adapted to send an interrupt packet over the switched serial connectionto the host interface to signal that the data have been transmitted,thus causing an interrupt input of the CPU to be asserted only after theone or more data packets have arrived at the host interface; wherein theinterrupt processor is adapted to send the interrupt packet afterreceiving an acknowledgment from the memory that the data have beenwritten thereto.
 6. Communication apparatus, comprising: a serialinterface, which is operative to receive data from a peripheral deviceand to transmit the data in the form of one or more data packets via aswitched serial connection to a host interface, for writing to a memoryassociated with a central processing unit (CPU) served by the hostinterface; and an interrupt processor, adapted to send an interruptpacket over the switched serial connection to the host interface tosignal that the data have been transmitted, thus causing an interruptinput of the CPU to be asserted only after the one or more data packetshave arrived at the host interface; wherein the serial interface iscoupled to send the data packets over a selected lane through thenetwork, and wherein the processor is adapted to send the interruptpacket over the selected lane following the data packets.
 7. Apparatusaccording to claim 6, wherein the switched serial connection comprises aswitch having a receive queue into which the serial interface places thedata packets, and wherein the interrupt processor is adapted to placethe interrupt packet into the receive queue following the data packets.8. Communication apparatus, comprising: a serial interface, which isoperative to receive data from a peripheral device and to transmit thedata in the form of one or more data packets via a switched serialconnection to a host interface, for writing to a memory associated witha central processing unit (CPU) served by the host interface; and aninterrupt processor, adapted to send an interrupt packet over theswitched serial connection to the host interface to signal that the datahave been transmitted, thus causing an interrupt input of the CPU to beasserted only after the one or more data packets have arrived at thehost interface; wherein the switched serial connection is part of aswitching fabric.
 9. Communication apparatus, comprising: a hostadapter, which is operative to receive data packets transmitted over aswitched serial connection from a peripheral device, and to convey datafrom the packets for delivery to a memory associated with a CPU over alocal bus that is coupled to the memory and the CPU, and further toreceive an interrupt packet sent over the switched serial connectionresponsive to an interrupt signal asserted by the peripheral deviceafter sending the data to the memory; and a host interface processor,adapted, responsive to the interrupt packet, to notify the CPU when allof the data have been conveyed to the local bus; wherein the hostadapter is operative to convey the data to the memory by direct memoryaccess.
 10. Communication apparatus, comprising: a host adapter, whichis operative to receive data packets transmitted over a switched serialconnection from a peripheral device, and to convey data from the packetsfor delivery to a memory associated with a CPU over a local bus that iscoupled to the memory and the CPU, and further to receive an interruptpacket sent over the switched serial connection responsive to aninterrupt signal asserted by the peripheral device after sending thedata to the memory; and a host interface processor, adapted, responsiveto the interrupt packet, to notify the CPU when all of the data havebeen conveyed to the local bus; wherein the switched serial connectionis part of a switching fabric.